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This paper presents a new system level power estimation methodology based on transaction level modeling for costum reconfigurable cores. The methodology can lead to significant improvement in trade-off between accuracy and efficiency of power estimation at system level. A SystemC based simulation environment is presented that allows rapid introduction of a power model into the executable specification...
A new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer'sA new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designer's productivity. SystemC is used as a system level language to raise the abstraction level for embedded systems design and verification...
In this paper we propose a novel framework for modelling heterogeneous SoC architectures with emphasis on reconfigurable component integration and optimised communication media. Our work targets three major issues faced by the current SoC design methodologies; a novel hybrid communication topology, communication centric platforms and modelling of reconfigurable components in the system. Multi-standard...
A new system-level approach is needed to incorporate re-configurability in IP-integration design flow, in order to speed up the designer's productivity. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part...
This paper proposes a hybrid communication medium for on-chip communication targeting adaptive SoC architectures. Unlike the work carried out in literature, where the term "hybrid" is used for the existence of more then one topologies for communication, the novelty of the proposed medium lies in combining two different communication media. In this paper, global bus and crossbars co-exist...
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity under control. Intellectual property reuse has been commonly employed as a technique to address this problem, but a new system-level approach is needed to integrate IP-Reuse methodology in the design flow, in order to speed...
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