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For the first time this paper makes an attempt at predicting the System-on-Chip (SoC) performance (i.e. logic, SRAM, ESD and I/O) of various sub 20 nm channel length planar and non-planar SOI devices using extensive & well calibrated 3D device and mixed-mode TCAD simulations. It has been shown that the non-planar devices such as FinFETs are not the ideal choice for SoC applications and perform...
Gate misalignment and process variations are important challenges in sub-20 nm gate length planar double-gate (DG) MOSFET devices. For the first time, we demonstrate a misalignment- and process variations-aware device optimization strategy for a DG-MOSFET. Using underlaps and high-kappa offset-spacers, we show that the robustness of the device to gate misalignment and process variations can be improved...
Sub-20 nm gate length FinFETs, are constrained by the very thin fin thickness (TFIN) necessary to maintain acceptable short-channel performance. For the 45 nm technology node and below, a novel device design methodology for undoped underlapped FinFETs with high-kappa spacers is presented to achieve higher circuit speed and SRAM cells with higher stability, lower leakage, faster access times and higher...
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