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We present an improved methodology to calibrate nominal SPICE models to individual or average PCM measurements at the die, wafer or lot level. The method overcomes previous difficulties in the structured handling of huge amounts of PCM data and it is validated in a state-of-the-art mixed-signal system-on-chip product development environment for the 65 nm CMOS technology node. The proposed approach...
The temperature dependency of silicided and blocked p-doped polysilicon resistors is examined in a 90 nm CMOS Flash technology. The blocked resistors are modeled in two portions to describe the silicided and the blocked regions separately. A process-control-monitor (PCM) like layout of the resistor test structures makes it possible to measure the resistance either in a lab environment manually or...
The effect of inhomogeneous negative bias temperature stress (NBTS) applied to p-MOS transistors under analog and RF CMOS operating conditions is investigated. Experimental data of a 0.18 and 0.25 μm standard CMOS process are presented and an analytical model is derived to physically explain the effect of stress on the device characteristics. The impact of inhomogeneous NBTS on device lifetime is...
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