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Dual-port SRAMs improve the performance of various hardware accelerators. This paper presents a low voltage 12T dual-port SRAM for biomedical hardware accelerators. The proposed dual-port SRAM cell -decreases the disturbance of the common-row-access mode for improving the worst case stability issue and realizing ultra-low voltage operation. In addition, hierarchical bitlines and a virtual ground technique...
A semi-active high-efficient (SA-HE) CMOS rectifier with reverse leakage control has been developed. It employs a cross-coupled NMOS pair and two leakage control comparators to reduce reverse charge leakage current. In addition, the adaptive body bias control technique is utilized to improve the reliability of the rectifier. The SA-HE rectifier has been fabricated in a 0.18um CMOS technology and shows...
A Software-Defined Radio (SDR) analog front-end is presented that provides extensive programmability of LO generator, LNA, mixers, baseband filters and PPA, supporting various wireless communication standards while guaranteeing a near-optimal power/performance trade-off at any time. The circuit is integrated in a 0.13 mum CMOS technology with 1.2 V supply voltage. This transceiver covers the frequency...
A fully reconfigurable SDR contains an RX, a TX, and 2 synthesizers for true multi-standard operation. A MEMS-enabled dual-band LNA proves the feasibility of switched antenna filtering for interference robustness. The baseband section is programmable in noise level and in bandwidth from 350kHz to 23MHz. The receiver has 6dB NF, -9dBm IIP3, and up to 90dB gain. Implemented in a 0.13μmum CMOS process,...
Negative Bias Temperature Instability (NBTI) is one of the most critical device reliability issues facing scaled CMOS technology. In order to better understand the characteristics of this mechanism, accurate and efficient means of measuring its effects must be explored. In this work, we describe an on-chip NBTI degradation sensor using two delay-locked loops (DLL). The increase in PMOS transistor...
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