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Time Dependent Dielectric Breakdown (TDDB) in p-FETs with HfSiON/SiO2 gate stacks under negative bias stress has been studied. It is shown that the shape parameter of Weibull distribution of Tbd, β, is very small value independent of gate electrode materials. This small β seems to arise from the interface layer (I.L.) breakdown. Further experimental result reveals the existence of additional interface...
Mobility (??) and Lg dependence of high-field velocity (v) is systematically investigated. A wide variety of ?? characteristics are realized with various gate dielectrics of SiO2, SiON, HfLaSiON, and HfLaAlSiON. At Lg = 30 nm, the sensitivities of v to ?? and scaling in Lg, (??v/v)/(????/??) and (??v/v)/(??Lg/Lg), are 0.43 and -0.45, respectively: in quasi-ballistic transport regime, ?? and scaling...
Intrinsic correlation between mobility reduction by remote Coulomb scattering (RCS) and threshold voltage shift (DeltaVt), both of which are induced by interface dipole modulation at high-k/SiO2 interface, is investigated. Three types of dipole modulation are examined; Al addition, La addition, and changing quality of interfacial SiO2 layer. Extrinsic scattering components due to increases of interface...
We report TaCx/HfSiON gate stack CMOS device with simplified gate 1st process from the viewpoints of fixed charge generation and its impact on the device performance. Moderate Metal Gate / High-K dielectric (MG/HK) interface reaction is found to be a dominant factor to improve device performance. By optimizing TaCx composition, fixed charge free TaCx/HfSiON device is successfully fabricated. Also,...
To clarify mobility (mu) limiting factors in aggressively scaled metal gate (MG)/high-k insulator (HK) MOSFETs, additional mu components associated with TaC and TiN MGs and their physical origins are investigated. With a TaC/HfSiON stack, mu@Eeff=1MV/cm of 215 cm2/Vs, 87% of Poly Si/SiO2 universal, at EOT of 0.91nm is achieved. Two different types of additional scattering are, for the first time,...
Low temperature device operation at 240 - 300 K temperature range is a promising approach to extend the device technology. The guideline of device design for cooling CMOS and the optimum operation temperature considering total power consumption is discussed for the first time. Also, the compatibility of cooling CMOS with advanced high-k gate dielectrics and embedded SiGe S/D technique are clarified
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