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The lack of observability of prototype chips makes post silicon debug extremely difficult and time consuming. Trace based debug techniques can improve the observability by acquiring some internal states at runtime through a dedicated on-chip trace buffer. In this paper, we propose a flip-flop clustering based trace signal selection method, which uses the forward tracing to generate flip-flop clusters...
Through silicon measurements of test chips designed based on two standard cell libraries in 40nm, this paper shows that by proper current distribution balancing between NMOS and PMOS network, standard cells can be improved in terms of speed, power efficiency and variation resilience in sub-threshold region. Compared to the commercial library cells, combinational cells have 2× better speed at sub-threshold...
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