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Cyber-physical systems (CPS) integrate computation with physical processes. For the last years, CPS have been in the focus of research and are getting adopted in multiple domains like health care, automotive and smart factories. The use of CPS promises dynamic adaption of systems to changing environmental and economic conditions through autonomous CPS decisions based on the physical process. In industrial...
This paper presents an ultra-wideband single-chip radar transceiver MMIC around 240 GHz in a SiGe:C bipolar laboratory technology with an fT of 240 GHz and fmax of 380 GHz. The presented transceiver architecture consists of a fundamental 120 GHz VCO, two 240 GHz frequency doublers, a fundamental 240 GHz down-conversion mixer, a divide-by-four stage, a PLL-mixer and two on-chip patch antennas. The...
Real-time scheduling in systems with energy or power constraints is challenging. Especially when a mixture of real-time and best effort tasks exist, it is difficult to guarantee that all deadlines are met and at the same time that the system does not run out of energy. This is the case for industrial instrumentation for hazardous areas, such as explosive atmospheres. A frequently used method of protection...
This paper presents two differential signal source chips for 150 GHz and 220 GHz in SiGe:C bipolar technologies. The presented architectures consist of a fundamental VCO with a frequency doubling output stage based on the differential Gilbert-Cell. The 150 GHz chip is fabricated in a production technology with an fT of 170 GHz and fmax of 250 GHz, the 220 GHz in an advanced laboratory technology with...
In this paper we present an efficient hardware architecture for accelerating the Robust Header Compression version 2 (ROHCv2) algorithm in Long Term Evolution (LTE) mobile devices. The proposed hardware accelerator and its software variant are evaluated on an FPGA-based SoC. Our results show that the advised hardware architecture provides processing speeds (2.9 Gbit/s) beyond LTE-Advanced. Moreover,...
This paper presents an ultra-wideband signal source chip for the D-Band in a SiGe:C bipolar production technology with an ƒT of 170 GHz and ƒmax of 250 GHz. The presented architecture consists of a fundamental VCO with a frequency doubling output stage. The goal of this work is to achieve a signal source near the technologies cut-off frequency while providing good performance concerning phase noise,...
In this paper we present a versatile hardware architecture for accelerating the Long Term Evolution (LTE) integrity protection and confidentiality algorithms based on SNOW3G and ZUC stream ciphers. The proposed design combines both ciphers in a unified configurable hardware accelerator unit and focuses on area and energy consumption reduction, by applying resource sharing and power optimization techniques...
In this paper we devise and compare several hardware implementations of the confidentiality algorithm that is based on the ZUC stream cipher. First we design and analyze a reference architecture, which reflects a basic implementation of the algorithm, with respect to power and area consumption in order to identify design's bottlenecks. Then different architectures for the most power demanding operations...
In this paper a monostatic fully integrated singlechannel SiGe transceiver chip around a center frequency of 24 GHz is presented. The architecture consists of a fundamental VCO, a receive mixer, a divider chain, and coupling/matching networks. All circuits, except for the divider, are designed with the extensive use of on-chip monolithic integrated spiral inductors. The chip is fabricated in a SiGe...
In this paper, we present different acceleration concepts for the Robust Header Compression version 2 (ROHCv2) algorithms in Long Term Evolution (LTE) handsets. First, we explore the potential performance improvements and energy savings by adopting scratchpad memories at various sizes. Second, dedicated hardware accelerators with different data transfer modes are compared in terms of processing speed...
In this paper we present an efficient software implementation of the Advanced Encryption Standard (AES) used in the confidentiality algorithm of the Long Term Evolution (LTE) protocol. Our implementation is based on slicing and merging the bytes of several data blocks to exploit processor's architecture width for multi-block encryption. In addition, an appropriate lookup table and data organization...
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