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In this paper, through silicon via (TSV) based interposer fabrication processes for 3D stack packaging has been presented. An interposer test chip of 25 ?? 25 mm size, has been designed with full array TSVs of 50 um size vias at 300 um pitch. TSVs of aspect ratio 4 are formed on 8 inch wafer using DRIE process and these vias are isolated by thermal oxide, followed by barrier/seed layer of Ti/Cu deposition...
A novel dual etch process technology has been demonstrated which provides an opportunity to precisely and independently control the etch throughput and required via slope that is required to achieve conformal deposition of dielectric, copper diffusion barrier and copper seed metallization. It is further shown how a void-free copper via plating has been achieved for implementation into 3-D integrated...
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