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A kind of image processing with a low power dynamically reconfigurable processor array (DRPA) prototype MuCCRA-3 implemented with 65 nm CMOS process will be shown. The measured power is also exhibited during execution, and compared with Xilinx Virtex-5 FPGA using exactly the same environment. The demonstration shows that more than 10 times better power efficient computation is achieved using MuCCRA-3...
Today's cellular phones must support full high-definition (full-HD) video in multiple video formats, such as H.264 and MPEG-2/-4, with low power consumption. Full-HD video processing requires six times the data bandwidth and is more computationally intensive than conventional standard-definition (SD) video. The trade-off between flexibility, performance and power consumption is a key focus of video-codec...
A full high-definition (full HD) video codec includes a high-performance stream processing unit to support multiple standards in mobile application processors. The unit performs at 40 Mbps when operated at a 162-MHz clock rate. Implemented in 65-nm CMOS technology, the proposed video codec consumes 176 mW in real-time decoding of H.264 full HD video.
This paper proposes a multi-drop on-chip transmission line interconnect for high-speed on-chip buses. The proposed two-way transceiver serves as both Tx and Rx for on-chip transmission lines and can branch signals without delay degradation. The proposed interconnect, which has six two-way transceivers and 5-mm-long transmission line, performs 8 Gbps signaling with power dissipation of 7.1 mW.
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