The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
On-chip linear decompression-based schemes have been widely adopted by industrial circuits nowadays to effectively reduce the ever increasing test data volume and test time. Though they can easily achieve relatively high compression ratio, there is a bound of effective compression ratio for these compression schemes. Prior work tried to address this problem by trying different compression architectures...
This paper proposes to provide testability for the breaking point produced by the Through-Silicon-Vias (TSVs) of 3D-Stacked ICs (3D-SICs) during pre-bond testing with low Design-for-Testability (DfT) cost. Different from prior solutions which utilize two additional wrapper cells for the breaking point at each TSV, this paper proposes to provide the testability of two ends of the TSVs respectively...
Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ldquodonpsilat-carerdquo bits can be exploited for test data compression and/or test power reduction. Prior work either targets only one of these two issues or considers to reduce test data volume and scan shift power together...
In scan-based tests, power consumptions in both shift and capture phases may be significantly higher than that in normal mode, which threatens circuits' reliability during manufacturing test. In this paper, by analyzing the impact of X-bits on circuit switching activities, we present an X-filling technique that can decrease both shift- and capture-power to guarantees the reliability of scan tests,...
Power consumption in scan-based testing is a major concern nowadays. In this paper, we present a new X-fllling technique to reduce both shift power and capture power during scan tests, namely LSC-filling. The basic idea is to use as few as possible X-bits to keep the capture power under the peak power limit of the circuit under test (CUT), while using the remaining X-bits to reduce the shift power...
Testing NoC-based systems mainly relies on reusing the Network-on-Chip architecture as the test access mechanism (TAM). This, however, implies that the core's test wrapper is supplied with full NoC channel width even if there is a mismatch between the two. How to effectively and efficiently make better utilization of the NoC channels for test data transferring is therefore an interesting and challenging...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.