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We have developed a new III-V self-aligned Quantum-Well MOSFET (QW-MOSFET) architecture that features a scalable highly conducting ledge over the channel access region. The extensive use of RIE and digital etching techniques enables the precise design of the length and thickness of the ledge and allows the careful balancing of performance against short-channel effects. We demonstrate Lg=70 nm InAs...
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to...
In this paper, the effects of nanowire (NW) line-edge roughness (LER) in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) are investigated by 3-D statistical simulation in terms of both performance variation and mean value degradation. A physical model is developed for NW LER induced performance degradation in SNWTs for the first time. The results indicate large performance mean value degradations...
The silicon nanowire MOSFET (SNWT) with gate-all-around (GAA) architecture has exhibited great potential in high-performance nano-electronics applications. However, line-edge roughness (LER) induced by lithography and etching processes has become a critical concern for decananometer MOSFETs, because it does not scale accordingly with line widths. Especially, the LER of nanowires, which contains two...
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