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In this paper a 12 bits 50 kS/s micropower hybrid ADC is proposed for biomimetic microelectronic systems using 0.18 mum CMOS process. The hybrid ADC combines SAR and dual-slope architectures to achieve 12 bits, power consumption 60 muW, and small silicon die size. This hybrid ADC shows very good figure-of-merits (FOM) on both power consumption and silicon die size compared with conventional low power...
Charge-metering microstimulator has been shown with higher charge accuracy, less charge-imbalance, and higher power efficiency than conventional current-mode and voltage-mode stimulators. In this paper, a discrete-time charge-metering microstimulator is proposed for implantable prosthetic device. Design techniques like half-clock sampling, high-voltage isolation, integration folding, and periodic...
A novel architecture to realize a low-power, low-noise amplifier for cortical neural prostheses is presented. The design consists of a low-noise variable gain amplifier as the first stage, a low-Gm high-pass filter as the second stage, and a low-pass Gm-C amplifier as the last stage. Discrete-time autozeroing is utilized to reduce the offset and noise. The bandwidth and autozeroing frequency of the...
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