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An arbitrary-input pulsewidth control loop (AIPWCL) based on a delay-locked loop with duty cycle corrector is presented. The duty cycles of the clock signals can be adjusted from 10% to 90% in 10% steps. The proposed AIPWCL is designed and simulated by using tsmc 0.13 mum CMOS process. The operation frequency range is from 770 MHz to 1.05 GHz. The locking time of AIPWCL is less than 40 ns within the...
A pulsewidth control loop (PWCL) based on a delay-locked loop (DLL) is presented in the paper. The duty cycle of the proposed PWCL can be adjusted from 10% to 90% in 10% step. The circuit is designed and simulated using TSMC 0.13 mum CMOS process. The operation frequency range is from 770 MHz to 1.43 GHz. The locking time of DLL is less than 15 ns within the operation frequency band. The power dissipation...
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