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Three-dimensional integrated circuits (3D-ICs) packaging has attracted a lots of attentions due to it has advantages of integrating heterogeneous functions among stacked chips. The thermal mismatch stresses with regard to interconnects composed through silicon via (TSV) and microbump induced by thermal cycling loads becomes a serious concern while a thinner stacked die thickness is required. To shrink...
To investigate the combined strained effects of dummy active diffused region (OD) and salient gate width of layout pattern on the mobility gain of nano-scaled device while advanced stressors of source/drain embedded silicon-carbon alloy and a tensile contact etch stop layers (CESL) are taken into account, the study uses a validated fabricated-oriented stress simulated methodology to estimate the performance...
A novel assembly process was developed for ultra-thin chip stacking technology where wafer-level-packaging (WLP) was adopted and combined with chip-on-wafer (CoW) technology. By such assembly process, thin chip handling would be unnecessary in this process. After assembly process, chip thickness within the chip stack could be thinned down to a thickness of 30µm or less than 30µm. Sheet-type molding...
A polymer waveguide combined with three silicon 45° micro-reflectors is realized on a silicon substrate to form a 1 × 2 vertically optical splitter with a 20-Gbps transmission rate for on-chip optical interconnect application.
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