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High-density and low-leakage 1W1R 2-port (2P) SRAM is realized by 6T 1-port SRAM bitcell with double pumping internal clock in 16 nm FinFET technology. Proposed clock generator with address latch circuit enables robust timing design without sever setup/hold margin. We designed a 256 kb 1W1R 2P SRAM macro which achieves the highest density of 6.05 Mb/mm2. Measured data shows that a 313 ps of read-access-time...
An embedded SRAM power management scheme using 16 nm FinFET technology is demonstrated in automotive infotainment SoCs. By introducing write-assist circuit technique, SRAM can operate down to 0.5 V wide voltage range, achieving DVFS for efficient power saving. Fast resume standby mode is also developed for reducing the leakage power of L1 cache under 2 GHz CPU operation. We confirmed that proposed...
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