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In this Letter, a highly reliable automotive integrated protection circuit for human body model electrostatic discharge (ESD) of + 6 kV with an over voltage of 8.2–16 V and a reverse voltage of −16 to 0 V is presented. In the automotive application, the reliability of the electronic device is important. In order to increase the reliability, a protection circuit is proposed to preserve the chip from...
The ElectroLuminescent (EL) panel is an emerging backplane lighting technology for advertising displays and facade (building) decoration. Compared to conventional lighting technologies, the major advantages of the emerging EL panel include large panel format (e.g. >100m2), significantly more-even illumination uniformity, (mechanical) flexibility, thinner form-factor, etc. As EL lighting is emerging,...
In this paper, we describe the fundamental study of the block-parallel analog signal processing elements which includes CMOS image sensor, correlated double sampling (CDS) array, and analog-to-digital converter (ADC) array. To realize high-speed image capturing sensor, we have proposed a blockparallel signal processing with three-dimensional (3-D) structure. In proposed system, one block consists...
This paper presents a low power VLSI implementation of a novel Multiple-Input Multiple-Output (MIMO) decoder which combines Fixed Complexity Sphere Decoder (FSD) algorithm, real-valued lattice formulation and Pair-wise sorted QR decomposition (P-SQRD) searching approach to simultaneously improve the throughput, bit error rate (BER) and complexity. Two-stage approximate sorting scheme with minimum...
This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated...
We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-based contention algorithm is proposed, modeling in VHDL for high-speed cell scheduler of ATM switching. A digital Hopfield neural cell scheduler which has the ability of real-time processing is used to solve loss of throughput...
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