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In this paper, we present an array of 160x128 pixels capable of detecting the ToA of single photons, implemented in 0.13μm CMOS technology. The sensor is partitioned into 4 identical quadrants that are served by a balanced clock tree so as to minimize skews and to ensure the fastest possible readout process. The pixels in the rows are read out in rolling shutter mode in two directions (top and bottom)...
A Time-to-Amplitude Converter (TAC) with embedded analog-to-digital conversion is implemented in a 130-nm CMOS imaging technology. The proposed module is conceived for Single-Photon Avalanche Diode imagers and can operate both as a TAC or as an analog counter, thus allowing both time-correlated or time-uncorrelated imaging operation. A single-ramp, 8-bit ADC with two memory banks to allow high-speed,...
We report the design and characterisation of a 32times32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130 nm imaging process. Based on a gated ring oscillator approach, the 10 bit, 50 mum pitch TDC array exhibits a minimum time resolution of 50 ps, with accuracy of plusmn0.5 LSB DNL and 2.4 LSB INL. Process, voltage and temperature compensation...
A new integration based fluorescence lifetime imaging microscopy (FLIM) called IEM has been proposed to implement lifetime calculations. A real-time hardware implementation of this IEM FLIM algorithm suitable for a single photon avalanche diode (SPAD) array in 0.13 mum CMOS technology is now implemented on FPGA. A widefield microscope was adapted to accommodate the array and test it on biological...
We report on a new single photon avalanche diode (SPAD) fabricated in a 130 nm CMOS imaging process. A novel circular structure combining shallow trench isolation (STI) and a passivation implant creates an effective guard ring against premature edge breakdown. Thanks to this guard ring, unprecedented levels of miniaturization may be reached at no cost of added noise, decreased sensitivity or timing...
A 2/3" 5 /spl mu/m/spl times/5 /spl mu/m pixel HDTV imager in a 0.25 /spl mu/m CMOS process uses a tapered reset technique to suppress kT/C noise and supply 12b video with <15 e-read noise at 60, 72 and 90 Hz frame rates. Peak S/N ratio at 90 Hz (225 MHz video rate; 2.7 Gb/s at 12b/pixel) is 52 dB at standard scene illumination. Random noise at 18 dB gain is 8e-, independent of video frequency.
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