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Schottky Barrier MOSFETs were fabricated on ultra thin body (UTB) SOI with planar and NW-array device geometry. Implantation into Silicide (IIS) was used to lower the Schottky Barrier height for n- and p-type MOSFETs. The enhanced gate control of the NW array reduces Drain Induced Barrier Lowering (DIBL) and improves the subthreshold slope in n-type MOSFETs, whereas the corrected current drops. In...
This paper presents experimental results on metal oxide semiconductor field-effect transistors (MOSFETs) featuring an array of 1000 trigated uniaxially strained nanowires with a cross-sections of 15 × 15 nm2 in combination with a HfO2/TiN gate stack. The high uniaxial strain along the wires reduces the band gap energy by approximately 140 meV and enhances the electron mobility. Ideal inverse subthreshold...
Tunneling field-effect transistors (TFETs) were fabricated from compressively strained Si/SiGe wafers with a stepped gate to enhance band to band tunneling. In-situ highly p-doped Si0.5Ge0.5 was used as source and As-implanted Si as drain. For the gate stack, conformal HfO2 (k = 22) and TiN were deposited, which resulted in an effective oxide thickness (EOT) of ∼ 1nm. The TFET devices exhibit minimum...
This letter presents experimental results on tunneling field-effect transistors featuring arrays of -gated uniaxially strained and unstrained silicon nanowires. The gate control of a gate stack is compared with a high-/metal gate stack. Steep inverse subthreshold slopes down to 76 mV/dec and relatively high on -currents were achieved with the combination of high-...
Compressively strained Si1-xGex band-to-band tunneling field effect transistors with planar structure and HfO2/TiN gate stack have been produced and analyzed, with different Germanium concentrations of x = 0.35, 0.50 and 0.65. Simulations using a nonlocal band-to-band-tunneling model have been carried out to understand the switching behavior and its dependence on the material parameters. One would...
P-MOSFETs with HfO2 gate dielectric and TiN metal gate were fabricated on compressively strained SiGe layers with a Ge content of 50 at.% and electrically characterized. The devices showed good output and transfer characteristics. The hole mobility, extracted by a split C-V technique, presents a value of ~200 cm2/V·s in the strong inversion regime.
The implementation of more powerful materials into leading edge CMOS devices allows performance improvements without scaling and without changing the circuit design libraries. This highly motivates the research on novel materials. In this paper we present various transistor fabrication processes like “gate first” and “replacement gate” for different channel stack configurations like strained Si, strained...
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