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To reach future low power operation at ⩽0.5 V, high mobility InGaAs nMOS and Ge pMOS were proposed at sub-14 nm nodes. However, the integration of InGaAs on Si faces difficult challenges of the large 8% lattice-mismatch, high dislocation densities, and antiphase domain boundaries. Although the defect-free Ge-on-Insulator (GOI), ultra-thin-body (UTB) InGaAs IIIV-on-Insulator (IIIVOI) on Si, and selective...
Reliability issues including random telegraph noise (RTN) and program disturbance in floating gate (FG) NAND strings for different junction dosages are compared. Although the initial threshold voltage (VT) distributions are similar for various source/drain (S/D) dosages, these samples exhibit different amplitudes on read current fluctuation. This current noise will induce inaccuracy in sensing level...
Source/Drain Reliability issues in a floating gate (FG) NAND string with different junction dosages are investigated. A lighter junction dosage gets better sub-threshold swing (SS) and helps the shrinkage of device channel length. However, some drawbacks, such as worse current fluctuation and abnormal self-boosting (SB), can be observed as the side effects. Charge pumping technique is applied to identify...
Gate stack etch profile-induced reliability issues are reviewed and discussed. A taper nitride profile, which blocks source/drain (S/D) implantation, induces an unwanted n- region. In other words, residual charges above the junctions can deplete the n- much easily and cut off the channel formation. This will cause poor string resistance distribution, worse endurance behavior, program and erase (P/E)...
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