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The fundamental question addressed in this paper is how to maintain the operation dependability of future chips built from forthcoming nano- (or subnano-) technologies characterized by the reduction of component dimensions, the increase of atomic fluctuations and the massive occurrence of physical defects. We focus on fault tolerance at the architectural level, and especially on fault-tolerance approaches,...
We address two problems in this work, namely, 1) the resilience challenge in the future chips made up of massively defective nanoelements and organized in replicative multicore architectures and 2) the issue of preserving the production yield. Our main suggestion is that the chip should be self-configuring at the architectural level, enabling with almost no external control mechanisms, core mutual-test...
We describe a self-configuration methodology to tolerate defective nodes in chips organized in massively replicative architectures as those shown below in Figure 1, made up of hundreds of cores in a highly defective technology. Note that the keyword of this presentation is not configuration but self-configuration. The basic idea is that chips will become so complex that it will be unrealistic to consider...
Many previous studies have analyzed the issues of dependability in the physical layers of future nanoarchitectures. Here we consider the upper layers and especially the contribution of communications to reinforcing the dependability of general-purpose nanoarchitectures (GPN). We adhere to the idea that a GPN should be viewed as a single-chip massive multiprocessor system, consisting in immersing a...
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