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We present a new method to identify multi-site implications that can significantly increase the fault coverage of error-detecting hardware without increasing the area overhead. This method intelligently divides the input space about the functions of internal circuit sites and finds new valuable implications that can share gates in checker logic.
Ensuring reliable computation at the nanoscale requires mechanisms to detect and correct errors during normal circuit operation. In this paper we propose a method for designing efficient online error detection schemes for circuits based on the identification of invariant relationships in hardware. More specifically, we present a technique that automatically identifies multi-cycle gate-level invariant...
As the complexity of integrated circuits has increased, so has the need for improving testing efficiency. Unfortunately, the types of defects are also becoming more complex, which in turn makes simple approaches for testing inadequate. Using n-detect testing can improve detect coverage; however, this approach can greatly increase the test set size. In this proof-of-concept paper we investigate the...
In this paper, we investigate the use of logic implications for the online detection of intermittent faults and hard-to-detect manufacturing defects. We present techniques to efficiently identify the most powerful circuit implications that can be checked for violations so that the fraction of errors detected can be maximized while minimizing the additional hardware overhead. Importantly, our approach...
Defective part levels of zero are almost impossible to achieve in an era of complex defects, process variations, and limited testing resources. It is important to ensure that any defects missed during test will impact the end user as little as possible. However, optimizing test sets for superior detection of critical defects requires an understanding of relative fault criticality, and this determination...
Power consumption during scan-based test becomes a concern in nanometer technologies. Previous test power reduction techniques that insert additional logic in gate-level circuits may result in timing violations. In this paper, we show that the problem can be solved at the RTL instead so that the timing and area constraints will be handled automatically by synthesis tools. Using a signal probabilistic...
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