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A methodology has been proposed recently to predict error rates of cascade structures of blocks in Probabilistic CMOS (PCMOS). It requires characterization of unique probabilistic blocks to predict the error rates of a multi-block cascade structure. While the technique was shown to work for a probabilistic carry-select adder, the technique needs a new model to work in a Wallace Tree Multiplier (WTM)...
Due to the requirement of high data transmission rate, bandwidth has become an important performance parameter for high speed VLSI design. In order to have the maximum data transfer possible through the on-chip data buses, the bandwidth of the interconnect has to be precisely modeled. At very high frequency (of the order of few GHz) both inductance and conductance matrices become equally important...
This paper presents a systematic, hierarchical, optimization based semi-formal equivalence checking methodology for large analog/mixed signal systems such as PLLs, ADCs and I/O's. We verify the equivalence between a behavioral model and its electrical implementation over a limited, but highly likely, input space defined as the Constrained Behavioral Input Space. Further, we clearly distinguish between...
Aggressive scaling of CMOS technology has enabled faster and smaller designs but has posed new challenges. In the deep-submicron era, leakage power has become a major contributor to the overall power dissipation of an IC. In this paper, we present a weighted partial Max-SAT (WPMax-SAT) based approach to find the minimum leakage vector (MLV) of a combinational design. In its exact form, this technique...
In this paper, we have derived a closed form formula for the power dissipation in highly coupled distributed RLCG interconnects taking the mutual inductive coupling into account. Power is increasingly becoming the bottleneck for the design of high performance VLSI circuits. It is essential to analyze how the various components of power are likely to scale in the future, thereby identifying the key...
This paper proposes a wave propagation based approach to derive crosstalk and delay between two coupled RLCG interconnects in the transform domain. The increase of clock frequency into the GHz range, coupled with longer length interconnects of small cross-section and low dielectric strength, can result in cross coupling effects between on-chip interconnects. The traditional analysis of crosstalk in...
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