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This paper highlights a 14nm Analog and RF technology based on a logic FinFET platform for the first time. An optimized RF device layout shows excellent Ft/Fmax of (314GHz/180GHz) and (285GHz/140GHz) for NFET and PFET respectively. A higher PFET RF performance compared to 28nm technology is due to a source/drain stressor mobility improvement. A benefit of better FinFET channel electrostatics can be...
A 2nd generation of Implant Free Quantum Well pFETs is presented in this work. SiGe25%-embedded Source/Drain was implemented, leading to an excellent short channel control and logic performance (1mA/um-ION@-1V). No narrow-width effect was found and a multi-VTH strategy is also offered. Performance of the strained-IFQW pFETs was finally demonstrated at lower VDD.
This work demonstrates the successful integration of 0.85nm-EOT Si0.45Ge0.55-pFETs using a gate first approach. An in-depth analysis, ranging from capacitor-level up to circuit-level is carried out, with systematic benchmarking to a conventional Si-channel reference. Outperforming the state-of-the-art Si0.55Ge0.45-pFETs, an ION of 630μA/μm at LG_POLY = 35nm with IOFF = 100nA/μm and VDD = -1V has been...
Cooling is important to keep the temperatures of the highly integrated silicon electronic devices and power devices e.g. power MOSFET, IGBT. Yamaguchi et al. have proposed a new scheme to cool down the devices by its own current named ldquoself-cooling devicerdquo, in which the cooling process uses Peltier effect. In the proposed scheme, we should use the materials that have high thermal conductivity,...
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