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A full-rate 10 Gb/s transceiver core employing a tri-state binary PD with 100ps gated digital output is implemented in a 90nm CMOS process. Direct drive from the VCO is utilized to eliminate the 10GHz clock buffer current. The RX exhibits a recovered-clock jitter of 906fsrms and an input sensitivity of 5.9mVpp. The TX generates a jitter of 5mUIrms. The chip consumes 250mW.
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