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A time-to-digital converter (TDC) is a key element for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. To build high-resolution TDCs, many researchers have focused on minimizing the unit delay of quantization. Vernier delay-line-based TDCs [1] are a good example. Their performance, however, is limited...
The first synchronous cyclic TDC is proposed in 28nm CMOS process. A novel 2x time amplifier whose gain is insensitive to variations and noise is proposed by using time conservative nature of the proposed synchronous time adder. The implemented 12b TDC occupies 0.01 mm2, consumes 820µW and it achieves 0.63ps of resolution over 2.6ns of input range.
Logic-to-memory interconnections by double-side mounting on ultra-thin 3D glass interposers with Through-Package-Vias (TPVs) achieves high bandwidth (BW) (>25.6GB per second), without the complex TSV processes in logic ICs, required for wide I/O 3D-IC stack. While this interposer/packaging technology offers several advantages including power delivery by enabling thick power-ground (P/G) planes,...
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