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Challenges of design window shrinkage in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O and ESD devices, and by developing ESD robustness and circuit performance co-design methodologies. Advanced ESD metrology methods are reviewed and their applications in providing key information for reliability modeling are investigated. Package and wafer...
This work focuses on characterization, modeling, and design of three different ESD protection devices for high-speed I/O applications in 45 nm silicon on insulator (SOI) technology. In this paper, the gated diode, the bulk substrate diode, and a double-well field-effect diode are evaluated using very fast transmission line pulse (VF-TLP) test method.
It is crucial to minimize the parasitic capacitance at a high-frequency I/O, found in applications such as high-speed serial links and radio receivers. Here, we study the bias-dependent capacitance of a poly-defined SOI diode-a popular ESD protection device according to C. Putnam et al. (2004), C. Entringer et al. (2005), M. Khazbinisky et al. (2005), S. Mitra et al. (2005), and S. Voidman et al....
We study the SOI poly-defined lateral diode and its optimization to achieve high second breakdown current, low resistance and low capacitance. A second breakdown current of more than 12 mA/mum is achieved. We present a novel failure mechanism for the diode wherein oxide breakdown occurs during a CDM-like event; floating the poly gate is shown to reduce this susceptibility. We also introduce a biasing...
In this paper we will present a new integrated SOI substrate diode structure for ESD protection of SOI I/O circuits that is built under the buried oxide of the SOI wafer using a standard CMOS process. We will show that the protection level can reach four times what is achieved by the standard-lateral SOI diode structure. We will also show device and process simulation results to understand the self-heating...
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