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An equalizer circuit which minimizes both crosstalk and ISI is applied to a receiver with a strongly-coupled 2-parallel 2drop single-ended microstrip SSTL memory channel. The crosstalk equalizer adds a crosstalk-canceling pulse to a victim receiver signal to make the signal crosstalk-free during the transition interval of an incoming signal. A DFE is used for ISI compensation. The equalization of...
A 7Gb/s single ended transceiver with low jitter and ISI is implemented in 40 nm DRAM process. DRAM optimized LC PLL achieves inductor Q of 3.86 and results in random jitter of 670 fs RMS. A clock tree regulator with closed loop replica path reduces low as well as high frequency noise. RX 2-tap hybrid DFE combining sampling and integration methods reduces power and area by 37% and 24%, compared to...
Demand for high-speed DRAM in graphics application pushes a single-ended I/O signaling to operate up to 6Gb/s. To maintain the speed increase, the GDDR5 specification shifts from GDDR3/4 with respect to forwarded clocking, data training for write and read de-skewing, clock training, channel-error detection, bank group and data coding. This work tackles challenges in GDDR5 such as clock jitter and...
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