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A new combination of long millisecond (1-2.5 ms) flash anneal at high peak temperature(1200-1300°C) and a new absorber with low deposition temperature (<;400°C) have been developed to generate highly activated (Rs~ 500 ohm/sq), sub-20 nm abrupt (≤ 3 nm/decade) N+ and P+ junction. This new approach also provides sub-2 nm N+ and P+ junction dopant motion control with multiple long ms-flash which...
The authors explored some of the challenges of the extremely thin SOI technology for mainstream CMOS. Faceted RSD was used to minimize parasitic capacitance. PFET performance is competitive with best bulk CMOS technologies, while NFET performance can be increased by further reduction in the series resistance. The impact of silicon thickness on the device variability was studied to quantify wafer uniformity...
We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced...
This paper reports a MEMS tunable capacitor with a new actuation principle. The new design adopts electrostatic actuation of an electrically floating movable dielectric. This enables us to achieve a high Q factor by eliminating the loss associated with springs in the RF signal path. Also, the design can achieve a high tuning range, by using additional actuation combs and thus eliminating the pull-in...
A refractive index buffer enhanced grating coupler in silicon-on-insulator (SOI) was demonstrated. By a PMMA cladding layer, the grating coupler with the efficiency of 44% and 3-dB bandwidth of > 40 nm was obtained.
A diffractive grating in silicon was demonstrated for near vertical off-chip coupling between Silicon-on-insulator (SOI) photonic nanowire and optical fiber. By simulation, the coupling efficiency of 46% from nanowire to fiber was predicted. Finally, the grating coupler with the efficiency of 25% and 3-dB bandwidth of 45 nm was obtained.
A new integration scheme is presented to solve device and manufacturing issues for extremely thin SOI (ETSOI) technology with high-k/metal gate. Source/drain and extensions are effectively doped by an implant-free process to successfully reduce series resistance below 200 Omegaldrm. A zero-silicon-loss process is developed to eliminate loss of thin SOI layer during gate and spacer processes, enabling...
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