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This paper uses the simplified charge-based EKV MOSFET model for studying the effects of total ionizing dose (TID) on analog parameters and figures-of-merit (FoMs) of 28nm bulk MOSFETs. These effects are demonstrated to be fully captured by the five key parameters of the simplified EKV model. The latter are extracted from the measured transfer characteristics at each TID. Despite the very few parameters,...
The DC performance of both n- and pMOSFETs fabricated in a commercial-grade 28 nm bulk CMOS process has been studied up to 1 Grad of total ionizing dose and at post-irradiation annealing. The aim is to assess the potential use of such an advanced CMOS technology in the forthcoming upgrade of the Large Hadron Collider at CERN. The total ionizing dose effects show limited influence in the drive current...
The Large Hadron Collider (LHC) running at CERN will soon be upgraded to increase its luminosity giving rise to radiations reaching the level of GigaRad Total Ionizing Dose (TID). This paper investigates the impact of such high radiation on transistors fabricated in a commercial 28 nm bulk CMOS process with the perspective of using it for the future silicon-based detectors. The DC electrical behavior...
The internal parasitic bipolar transistor plays an important role in the unclamped inductive switching (UIS) failure of superjunction MOSFET. To suppress the activation of parasitic transistor, an innovative structure was proposed which features a P-island with relatively high doping concentration at the top of P-column and a trench-type P+ contact. The avalanche point is localized at the P-island...
Charge trapping and wearout characteristics of self-aligned enhancement-mode GaAs nMOSFETs with silicon interface passivation layer and HfO2 gate oxide are systematically investigated at various time scales (from micro-seconds to seconds). Unlike high-kappa on silicon devices, both bulk trapping and interface trapping affect the PBTI (positive bias temperature instability) characteristics of nMOSFETs...
Research on high-k (HfO2) materials has been expanded significantly. However, MOSFETs with high-k gate dielectrics on silicon still have several problems with relatively low mobility of high-k devices in thin EOT regime compared to the universal curve. In this work, as an alternative of silicon substrate, InP and In0.53Ga0.47As has been studied. W e present the material and electrical characteristics...
We study the variability of the electrical characteristics of silicon-on-insulator (SOI) SB-MOSFETs. A new method by extracting the variation of the threshold voltage from a large number of devices with different SOI thicknesses enables determining the main sources of variability and distinguishing between them. It is found that the device-to-device variability is mainly due to the inherent variation...
Using a thin germanium interfacial passivation layer (IPL), for the first time we present surface channel n- and p-MOSFETs on GaAs substrate with TaN gate electrodes and HfO2 dielectric films. We used self-aligned and gate-last processes to fabricate MOSFETs on semi-insulating GaAs substrate. The electrical results from the buried channel and the surface channel-mode transistors are investigated....
The impact of the gate oxide and the silicon-on-insulator (SOI) body thickness on the electrical performance of SOI Schottky-barrier (SB) MOSFETs with fully nickel silicided source and drain contacts is experimentally investigated. The subthreshold swing S is extracted from the experimental data and serves as a measure for the carrier injection through the SBs. It is shown that decreasing the gate...
In this work, using Si interface passivation layer (IPL) we present the electrical characteristics of TaN/HfO2/GaAs both p-and n-MOSFET made on GaAs substrates with excellent electrical and reliability characteristics, thin EOT (~2.3-3.0nm), low frequency dispersion (< 5%) and high maximum mobility (1213 cm2/V-s) with high temperature PMA for n-MOSFET on undoped GaAs. Good inversion behavior with...
To overcome the issues of mobility degradation and charge trapping in the high-k MOSFET, a stacked Y2O3 (top)/HfO2 (bottom) multi-metal gate dielectric with TaN gate has been developed. Compared to the HfO2 reference, the new dielectric shows similar scalability, but superior device performance and reliability characteristics. Channel mobility, fast transient charge trapping, bias temperature instability,...
Schottky barrier height engineering by silicidation induced impurity segregation is demonstrated. The segregation of sulfur at the NiSi/Si interface leads to a gradual decrease of the SBH on n-Si(100) from 0.65 eV to 0.07 eV, and correspondingly, to an increase of the SBH on p-Si(100). Alternatively, the effective SBH of NiSi is reduced by As and B segregation during silicidation. Using these techniques,...
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