The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We have studied key parameters for controlling threshold voltage (Vth) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the Vth variation same...
For the first time, we illustrate the importance of process sequence for LaOx capped HfSiON/metal gate on performance, variability, scaling, interface quality and reliability. La diffusion to the high-k/low-k interface controls Vt, as well as strongly affects mobility, Nit and BTI. La diffusion is limited to the Si surface by employing SiON interface layer (IL) mitigating the issues of La-induced...
The origin of stress induced leakage current and defect generation process in the high-k/metal gate stacks under the substrate hot carrier stress and constant voltage stress is investigated. The data suggests that the defects responsible for the SILC increase are located near the high-k/SiO2 interface. Generation of these defects is mostly caused by the cold carriers injected from the inversion layer...
La-doped HfSiO samples showed lower Vth and Igate, which was attributed to the dipole formation at the high-k/SiO2 interface. With increasing SiOx content, significant mobility degradation was observed, most likely due to additional La- related charges in the interfacial layer. La-doped devices demonstrate better immunity in the PBTI test and low charge trapping efficiency compared to the control...
We demonstrate an amorphous higher-k (k>20) HfTiSiON gate dielectric for sub 32 nm node capable of low equivalent oxide thickness (EOT=0.84 nm). For the first time, we have addressed the thermodynamic instability of TiO2 containing gate dielectrics achieving an acceptably thin SiOx interface (0.7 nm) after 1070degC. 3-10times leakage current reduction is achieved with HfTiSiON vs. HfSiON due to...
After over 10 years of intensive study on high-k dielectric and metal gate electrode to replace silicon based materials (Si02 or SiON gate dielectric and polysilicon gate) in the complementary-metal-oxide-semiconductor (CMOS) application, it was claimed that hafnium based dielectric and metal gate are finally ready to be implemented in 45nm technology and beyond. It was reported that the minority...
The effect of F implantation combined with high quality bottom interfacial layer has been investigated in terms of threshold voltage reduction and improvement of device performance of TaCN/AlN/HfSiOx gate stacks for PMOS application. Threshold voltage becomes more positive as AlN, F implantation, and thermally grown interfacial layer steps are added. It is found that F accumulates near the interface...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.