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The origin of stress induced leakage current and defect generation process in the high-k/metal gate stacks under the substrate hot carrier stress and constant voltage stress is investigated. The data suggests that the defects responsible for the SILC increase are located near the high-k/SiO2 interface. Generation of these defects is mostly caused by the cold carriers injected from the inversion layer...
We report on new observations of hot carrier (HC) degradation in strained Si/Si1-xGex(x = 0.2 to 0.5) p-MOSFETs. By using low voltage current-voltage measurement coupled with carrier separation, we are able, for the first time, to easily distinguish the energy distribution of the interface traps. High-K dielectrics on SiGe p-channel show higher interface traps generation located close to conduction...
La-doped HfSiO samples showed lower Vth and Igate, which was attributed to the dipole formation at the high-k/SiO2 interface. With increasing SiOx content, significant mobility degradation was observed, most likely due to additional La- related charges in the interfacial layer. La-doped devices demonstrate better immunity in the PBTI test and low charge trapping efficiency compared to the control...
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