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The presented theoretical analysis of random telegraph signal (RTS) and 1/f noise data provides consistent interpretation of the measurement results allowing trap characteristics to be extracted and the atomic structure of oxide traps to be identified. We emphasize the critical role of the lattice structural relaxation associated with charge trapping/detrapping, which represents one of the major factors...
We report on the promise of dual channel materials using FinFETs for high-performance CMOS for sub 22 nm technology node. We demonstrate pFinFETs with all SiGe channel formed by Germanium condensation onto a Silicon-On-Insulator carrier wafer (SiGeOI) followed by cMOS processing. The devices exhibit 3.6X hole mobility enhancement over Silicon (100) while allowing for VTH control with single high-k...
We present a comprehensive description of the processes contributing to the electron capture/emission by bulk oxide traps, which allows for interpretation of RTS and 1/f noise data and extraction of the trap characteristics. It is shown that the electron capture/emission times could be controlled by the trap structural relaxation (caused by the trapped electrons) rather than by the electron tunneling...
We have studied key parameters for controlling threshold voltage (Vth) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the Vth variation same...
The origin of stress induced leakage current and defect generation process in the high-k/metal gate stacks under the substrate hot carrier stress and constant voltage stress is investigated. The data suggests that the defects responsible for the SILC increase are located near the high-k/SiO2 interface. Generation of these defects is mostly caused by the cold carriers injected from the inversion layer...
La-doped HfSiO samples showed lower Vth and Igate, which was attributed to the dipole formation at the high-k/SiO2 interface. With increasing SiOx content, significant mobility degradation was observed, most likely due to additional La- related charges in the interfacial layer. La-doped devices demonstrate better immunity in the PBTI test and low charge trapping efficiency compared to the control...
High-performance sub-60 nm Si/SiGe (Ge:~75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high-kappa/metal gate stacks with ~1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length (Lg) devices demonstrate not only controlled short channel effects, but also an excellent on-off current (Ion/Ioff) ratio (~5times10...
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