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This work presents a complementary metal-oxide-semiconductor-compatible top-down fabrication of Ge nanowires along with their integration into pMOSFETs with "HfO2/TaN" high-k/metal gate stacks. Lateral Ge wires down to 14 nm in diameter are achieved using a two-step dry etch process on a high-quality epitaxial Ge layer. To improve the interface quality between the Ge nanowire and the HfO...
In this work, we use scanning tunneling microscopy (STM) to study the localized degradation, breakdown and post-breakdown of a high-κ (HK) gate dielectric material, cerium oxide (CeO2) deposited directly on a silicon substrate. The novelty of the study lies in analyzing the breakdown phenomenon from a macroscopic metal-oxide-semiconductor (MOS) capacitor level to a very localized nanoscale breakdown...
Focused Ion Beam (FIB) milling has been widely used for the preparation of TEM specimens in both cross-section and plan view configurations. FIB induced damage is a non-negligible influence on making a thin and clear TEM specimen. Low-KV FIB is one of the solutions to reduce the ion beam damage created in current FIB operation system. An understanding of the type of FIB generated artifact on different...
In order to achieve aggressive scaling of the equivalent oxide thickness (EOT) and simultaneously reduce leakage currents in logic devices, silicon-based oxides (SiON / SiO2) have been replaced by physically thicker high-κ transition metal oxide thin films by many manufacturers starting from the 45 nm technology node. CMOS process compatibility, integration and reliability are the key issues to address...
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