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Tunnel oxide degradation in TANOS devices and its origins were investigated in terms of program, erase, and endurance device operation modes. It was found that the erase operation may cause significant tunnel oxide degradation, while the degradation due to program operation is negligible. In the erase and endurance modes, tunnel oxide degradation is primarily controlled by the process of electron...
This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32 nm LSTP applications: Vt < plusmn 0.45 V (at Lg = 60 nm) at EOT les 1.4 nm, with 105 times Jg reduction compared to SiO2. This scheme integrates several simplifications and improvements for the first time: single metal gate material, single channel...
We apply a systematic approach to identify a high-k/metal gate stack degradation mechanism. Our results demonstrate that the SiO2 interfacial layer controls the overall degradation and breakdown of the high-k gate stacks stressed in inversion. Defects contributing to the gate stack degradation are associated with the high-k/metal-induced oxygen vacancies in the interfacial layer.
The origin of stress induced leakage current and defect generation process in the high-k/metal gate stacks under the substrate hot carrier stress and constant voltage stress is investigated. The data suggests that the defects responsible for the SILC increase are located near the high-k/SiO2 interface. Generation of these defects is mostly caused by the cold carriers injected from the inversion layer...
For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1 nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4 nm) SiOx interface layer. A secondary mechanism, Ge doping (ges4%) in high-k, possibly by up diffusion, also results in higher leakage. With...
We demonstrate for the first time a gate first high-k/metal gate (MG) nFET with EOT = 0.74 nm (Tinv = 1.15 nm), low Vt = 0.30 V, high performance [Ion/IOff = 1310(muA/um) at 100(nA/um)], low leakage (> 200x reduction vs. SiO2/PolySi) and good PBTI. Low-k interface layer scaling and high-k La-doping enable this desirable EOT and Vt. SiON/HfLaSiON can give similar interface quality as SiO2/HfSiON...
A comprehensive study implementing a high-k/metal gate stack on Si(110) substrates has been performed, including a comparison of HfO2 and HfSiON, and compatibility with strain engineering. We demonstrate p-channel MOSFETs (pFETs) with optimized atomic layer deposited (ALD) HfO2 on Si(110) substrates with a ~ 3.3times high field hole mobility (μh) enhancement vs. a Si(100) substrate. On-state drain...
Extraction of the intrinsic NBTI degradation rate in the high-k pMOSFETs was found to require correction of the measured threshold voltage shift (DeltaVTH) for the fast transient charging contribution caused by the charge trapping in pre-existing defects in high-k films. The proposed analysis methodology leads to a significantly lower estimated lifetime than that obtained by the generally used approach...
The hysteresis and mobilities of 1nm EOT HfSiON dielectric on multi-gate MOSFET (MuGFET) with TiN metal gate were studied. We did not observe any drain current hysteresis. This is consistent with the same gate stack on planar bulk MOSFET. However, we found significant electron and hole mobility degradation for MuGFET compared to SiO2 control devices (up to -25%). The percentage of degradation is higher...
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