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We investigate the influence of additional dc current on response of CMOS THz detectors. A resistive self-mixing model calculation, shows that the voltage response of CMOS detectors increases significantly by applying a small dc current on the drain side of CMOS device. The calculation results are further verified by the experimental data from CMOS detectors at 0.65THz. The maximum voltage response...
For the first time, we report high performance hybrid channel ETSOI CMOS by integrating strained SiGe-channel (cSiGe) PFET with Si-channel NFET at 22nm groundrules. We demonstrate a record high speed ring oscillator (fan-out = 3) with delay of 8.5 ps/stage and 11.2 ps/stage at VDD = 0.9V and VDD = 0.7V, respectively, outperforming state-of-the-art finFET results. A novel “STI-last” integration scheme...
For the first time we report extremely thin SOI (ETSOI) CMOS with 22 nm gate length (LG) and sub-100 nm contacted gate pitch for system-on-chip (SoC) applications. Multi-Vt transistors are demonstrated with competitive drive currents (NFET/PFET) of 1150/1050 µA/µm at Ioff = 100 nA/µm for high performance (HP) and 920/880 µA/µm at Ioff = 1 nA/µm for low power (LP), respectively, at VDD = 1 V. High...
By leveraging on the wealth of Si-CMOS technology know-how and the largely available infrastructures, the fundamental photonic device building blocks and circuit integration platform, essential for the realization of the electronic-photonic integrated circuit (EPIC), have been successfully developed. This presentation gives an overview on the current status of this critical technology and provides...
We present UTBB devices with a gate length (LG) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). Back bias (Vbb) enables Vt modulation of more than 125mV with a Vbb of 0.9V and BOX thickness of 12nm. This demonstrates the importance and viability of the UTBB structure for multi-Vt and power management applications...
A new combination of long millisecond (1-2.5 ms) flash anneal at high peak temperature(1200-1300°C) and a new absorber with low deposition temperature (<;400°C) have been developed to generate highly activated (Rs~ 500 ohm/sq), sub-20 nm abrupt (≤ 3 nm/decade) N+ and P+ junction. This new approach also provides sub-2 nm N+ and P+ junction dopant motion control with multiple long ms-flash which...
The authors explored some of the challenges of the extremely thin SOI technology for mainstream CMOS. Faceted RSD was used to minimize parasitic capacitance. PFET performance is competitive with best bulk CMOS technologies, while NFET performance can be increased by further reduction in the series resistance. The impact of silicon thickness on the device variability was studied to quantify wafer uniformity...
We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced...
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