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We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for the first time in the industry, ultra high NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme which features reversed extension and SD diffusion formation is established to meet Vt roll-off requirement with excellent transistor performance...
A self aligned metal capping process for Copper damascene interconnect is newly developed in this study. A tungsten capping layer is selectively formed on the Cu interconnect using the preferential deposition phenomenon of W-CVD assisted by pre and post treatment. This technology is applied to 0.2 /spl mu/m bipolar-CMOS LSI with multilevel Cu interconnects, and then yield, reliability and operation...
Time-dependent dielectric breakdown (TDDB) of MIS and MIM capacitors with Cu electrodes is investigated. The dielectric breakdown lifetime strongly depends on (1) the material and (2) the electric field strength of the dielectrics in contact with the Cu anode, while the dependence of the TDDB lifetime on the dielectric thickness and the capacitor structure (single-layer or multilayer) is small. In...
The temperature of 1 micrometer dia spot on a conductor was measured for the first time and compared with the predictions of the simulation model and with the data obtained by the line resistance method. Experiments were carried out to determine the dependence of electromigration lifetime on current density and temperature with an accurate measurement of temperature. These data support that the parameters...
This paper reports a new open failure observed in high aspect ratio contacts and vias filled with blanket tungsten CVD film. This failure mode has been proved to be induced by the poor film quality of the sputtered glue layer at the bottom of a hole. Open failure in contacts has been suppressed by lowering the deposition temperature of the sputtered glue layer together with the optimization of CVD...
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