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A 4-Mb (512 K*8) CMOS SRAM that uses a 0.5- mu m quadruple-poly double-metal CMOS technology to attain 23-ns address access time with a single 5-V external supply voltage and a load capacitance of 30 pF is described. Current-mirror/PMOS cross-coupled cascade sense amplifier circuits with a noise-immune data-latch circuit are used. A polysilicon PMOS load memory cell enables a 0.5- mu A standby current...
A 1-Mb (256k*4/1M*1) CMOS SRAM (static random access memory), fabricated using a half-micron triple-poly double-metal CMOS technology, is reported. A 9-ns access time is attained with 5-V supply and 30-pF load capacitance. This access time has been achieved with a three-stage pMOS cross-coupled sense amplifier, 0.6- mu m high-performance MOSFETs, and an optimized internal supply voltage scheme. A...
A 25- mu m/sup 2/ poly-Si PMOS load SRAM (static random access memory) cell, called a PPL cell, has been developed. The cell has been excellent retention characteristics, high soft-error immunity, and low standby power. These advantages are achieved using poly-Si PMOS loads and cross-coupled stacked capacitors formed between the NMOS and the stacked poly-Si PMOS. A large poly-Si PMOS ON current lowers...
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