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We systematically studied short-channel mobility (μ) in SOI nanowire transistors (NW Tr.). The strain induced in the NW channel dominates short-L μ. μ of short-L <;110>; NW nFETs largely increases due to vertical compressive strain. We achieved further strain enhancement in NW channel by stress memorization technique (SMT). μ increase by SMT is much larger in NW Tr. than in planar Tr. In <;110>;...
We successfully reduced the parasitic resistance of nanowire transistors (NW Tr.) by raised S/D extensions with thin spacers (<;10nm). Id variations are suppressed by spacer thinning and parasitic capacitance increase is minimal. By adopting <;100> NW instead of <;110> NW, Ion = 1mA/μm for Ioff = 100nA/μm is achieved without stress techniques. Long-L mobility (μ) was systematically...
This paper reviews the carrier transport mechanisms and stress engineering in advanced nanoscale MOSFETs. First, carrier transport in bulk (100) and (110) MOSFETs is reviewed. Sub-band structure engineering to enhance mobility as well as ballistic current is also examined.
The relationships between velocity, v, and mobility, μ, are investigated to clarify the effectiveness of μ enhancement to increase v in short channel FETs with SiO2 as well as high-K gate dielectric. The v-μ relationships were extracted on the basis of accurate understanding of v-μ dependence of μ; vsub dependences of μ in high-K, high Nsub, and short-channel FETs were carefully studied and the deviations...
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