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A multi-step word-line control technology (MWC), combined with a new hierarchical cell SRAM architecture (HCA), has been developed to overcome rapid increase in random variability with no area penalty. A 40-nm-node 0.248-μm2-cell SRAM using a single power supply has been successfully fabricated, pushing up bit density to 2.98 Mb/mm2. MWC improved VDD_min@-6σ by 0.34 V and 0.22 V for read and write...
A new hierarchical cell SRAM architecture, combined with a multi-step word-line control technology, has been developed to overcome rapid increase in random variability with no area-penalty. A 40nm-node 0.248 μm2-cell SRAM using a single power supply has been successfully fabricated, pushing up bit-density to 2.98Mb/mm2.
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