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CHESS-2 (CMOS HV Evaluation for Strip Sensors) is a novel ASIC strip architecture designed to investigate the feasibility of using HV-CMOS MAPS (Monolithic Active Pixel Sensors) as alternative sensors for the ATLAS Phase-II Strip Tracker Upgrade. The ASIC is optimized for signal processing, hit pixel position encoding and readout. CHESS-2 includes three independent groups of 128 strips composed of...
The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more important than the package capacitor for chip...
Ring-type yield loss at wafer edge has been observed during flip-chip packaging process. The failure mechanism is attributed to the scrubber clean process step which generates a lot of charges. This in turn behaves like an electrostatic discharge (ESD) event and damages gate oxide of internal circuits. An equivalent circuit is proposed to analyze such a kind of ESD event and proves the importance...
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