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This paper describes suppression of current collapse by field-plate (FP) in AlGaN/GaN MOS-HEMTs. Current collapse reduction was confirmed for a multi-gate fingered MOS-HEMT with a total gate width of 10 mm. Moreover, we have fabricated a 5-A class MOS-HEMT with both gate-FP and source-FP (dual-FP), showing more complete suppression in current collapse as compared to that with only gate-FP.
This paper describes breakdown characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) with multi-finger gate patterns. We studied the spatial profile of electroluminescence (EL) from AlGaN/GaN HEMTs under high drain and near pinch-off gate bias. As a result, different EL emission profiles and breakdown characteristics were observed depending on the drain electrode pattern of the devices.
This paper describes the effect of thickening Au-plated ohmic electrodes in AlGaN/GaN HEMTs on the drain current and on-resistance. By increasing the thickness of Au-plated ohmic electrodes up to 5 µm, the fabricated AlGaN/GaN HEMT with a total gate width from 2 to 10 mm exhibited an increase in the maximum drain current by about 50 % and a reduction in the on-resistance by more than 40 %.
NAND flash memories are now indispensable for our modern lives. The application range of the storage memory devices began with digital still cameras and has been extended to USB memories, memory cards, MP3 players, cell phones including smart phones, netbooks, and so on. This is because higher storage capacity and lower cost are realized through means of technology scaling every year. Emerging markets,...
For the first time, we demonstrate standard cell gate density of 3650 KGate/mm2 and SRAM cell of 0.124 mum2 for 32 nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45 nm technology node, which is unattainable by dual exposure (DE) lithography or double patterning (DP)...
In this paper, an asynchronous high-speed logic circuitry using low temperature poly silicon-thin film transistor (LTPS-TFT) and the bootstrapped technology (BST) for liquid crystal display (LCD) is proposed. The proposed logic circuit operates at high frequency region owing to the deep non-saturation operation by using the bootstrapped technology. To confirm some characteristics of the proposed circuit,...
We develop an emulation system for performing experiments related to active tag based pedestrian localization. We use emulation as an integral part of our development approach so as to be able to carry out large-scale experiments with ease, and in a repeatable manner. Our demonstration will show how to perform live emulation experiments on a remote network testbed located in Ishikawa, Japan. The experimental...
This paper presents an architecture of digital wave filters for processing bit-stream signals with nanoelectronic devices. We use three kinds of circuit modules for the filters. One of the modules is an integer delay built of unit delay cells connected in series. The rest of the modules are two types of adders based on bit-sorting networks which are built by connecting ANDOR gate pair cells regularly...
A laser diode having a saturable absorber within its cavity is proposed as an optically triggered optical logic gate. A threshold characteristic, a small delay time, a short output pulse and a possibility of integration of the gate lasers are predicted by theoretical analysis.
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