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A 0.094μm2 8T SRAM bitcell is developed for a 14nm technology featuring FinFET transistors with a 70nm contacted gate pitch [1]. The bitcell and supporting circuitry are optimized for high density and aging tolerance. Supply collapse and wordline boosting techniques are applied for write VMIN assist. A delayed keeper is used for read VMIN improvement. A 400MHz VMIN of 560mV is achieved with the proposed...
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