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We present a novel fully-depleted SOI CMOS technology with dielectrically-isolated polysilicon back gates, achieved by a double BOX substrate combined with dual-depth shallow trench isolation. CMOS devices down to 30nm gate length are fabricated with high-κ/metal gates. A novel isolation structure with liners is shown to achieve robust isolation between devices and back gates. Effective back gate...
A 300-mm wafer-level three-dimensional integration (3DI) process using tungsten (W) through-silicon vias (TSVs) and hybrid Cu/adhesive wafer bonding is demonstrated. The W TSVs have fine pitch (5 mum), small critical dimension (1.5 mum), and high aspect ratio (17:1). A hybrid Cu/adhesive bonding approach, also called transfer-join (TJ) method, is used to interconnect the TSVs to a Cu BEOL in a bottom...
Recent progress in the metallization of poly-silicon thin-film solar cells on glass, created by solid phase crystallization (SPC) of evaporated amorphous silicon (EVA), revealed that this type of solar cell suffers from severe shunting problems when the air-side (i.e., rear) metal contact is deposited. Pinholes of sizes between 5 and 20 microns exist in this material at moderate density (0.1–1 mm−2...
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