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In this paper, we exemplify the power reduction that can be achieved by using analogue rather than digital signal processing. This reduction is illustrated with an FSK demodulation. The power reduction is achieved using conventional off-the-shelf discrete electronics components rather than through an ASIC implementation. The power consumption is reduced by a factor of more than ten; more specifically,...
A MIMO 3GPP-LTE digital baseband chip based on a heterogeneous 3 ?? 5 array NoC using 3.2 GOPS/50 mW programmable VLIW cores is presented. It features less than 10 ??s run-time full physical layer reconfiguration and distributed power management leading to 477 mW power consumption on a 4 ?? 2 MIMO RX application.
With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article...
This article aims at highlighting new design issues coming from the increasing sensitivity of digital circuits towards process variability. CAD tools and current design methodologies are not anymore efficient to tackle such aspects. In particular variability is increasing the difficulty to identify setup and hold time violations. This paper is a study of failure probabilities considering device process...
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