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Scan Compression has become an integral part of today's design-for-test (DFT) methodology for achieving high quality test at lower costs. Just as scan matured over a span of 40 years we are going to see Scan Compression improve. In this paper we present one such improvement to scan compression. An intelligent scan chain design for proactively managing the Xs in scan compression architectures is presented...
Scan compression technology combines the expected responses from multiple scan chains to be observed at fewer scan outputs. As a result unknowns (Xs) in the test response interfere with the good values that could be observed. Prior to this paper, Xs in the test response were treated as bad for compression and solutions either removed, bypassed, or blocked the Xs from interfering with the other responses...
The use of scan based compression techniques is becoming mandatory on current designs. While high compression is desired to hold the test costs within limits, it is important to understand the bounds set by the entropy of the care bits required by different compression techniques, to enable the selection of the right set of design and test parameters. This paper highlights the available solution space...
The beginnings of the modern-day IC test trace back to the introduction of such fundamental concepts as scan, stuck-at faults, and the D-algorithm. Since then, several subsequent technologies have made significant improvements to the state of the art. Today, IC test has evolved into a multifaceted industry that supports innovation. Scan compression technology has proven to be a powerful antidote to...
Testing today of a several hundred million transistor system-on-chip with analog, RF blocks, many processor cores and tens of memories is a huge task. What the test technology be like in year 2020 with hundreds of billions of transistors on a single chip? Can we get there with tweaks to today's technology? While the exact nature of the circuit styles, architectural innovations and product innovations...
Recent test-cost reduction methods are based on controlling the initial state (seed) of a pseudo-random pattern generator (PRPG) so that deterministic values are loaded in selected scan cells. Combined with an unload-data compression technique, PRPG seeding reduces test data volume and application time. This paper presents a method of mapping each scan load to multiple PRPG seeds, computed so that...
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