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A 21-GHz fractional-N PLL was demonstrated in 130-nm CMOS. The PLL consumes 19.6 mW power from a 1.2-V supply. The locking range is from 19 to 21.6 GHz, and the frequency resolution is 10 ppm. The measured in-band phase noise at 50-kHz offset and out-of-band phase noise at 20 MHz offset are -67.8 and -121 dBc/Hz.
A transmitter with an on-chip dipole antenna operating in the 24-GHz ISM band was fabricated in 130-nm CMOS. It provides 8-dBm output power and 7.7% rms EVM while consuming 100-mW power. An integer-N synthesizer consuming 36-mW power is also integrated. The signal transmitted by the chip has been picked up 95 m away using a horn antenna. This work demonstrates that communication between a base station...
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