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Analyzing power supply noise characteristics and predicting its jitter impact is critical in designing the 12.8Gbps single-ended memory interface achieving better than 5mW/Gbps energy efficiency. The clocking circuit jitter performance is characterized by jitter sensitivity. The power supply noise induced jitter (PSIJ) is derived by combining the noise spectrum and sensitivity profile. The final PSIJ...
High-speed link design in a 3D package system poses unique challenges due to the fact that it provides limited visibility to signal quality and that supply noise induced jitter is large due to a poor power distribution network in a small form factor. This paper outlines a statistical link simulation flow to accurately capture the impact of timing jitter due to power supply noise in 3D systems. The...
System power integrity characterization for low-power high-speed memory interface in a 3D package system is a challenging task due to probing difficulties imposed by small form factor. In this paper, power integrity measurements including supply noise, PSIJ sensitivity and PDN impedance curve using on-chip noise generator and monitors are presented. On-chip measurement data are validated by off-chip...
This paper experimentally investigates substrate noise and its impact on the jitter performance of a low-power memory controller PHY interface using an on-chip substrate noise measurement structure. A previously proven on-chip supply noise measurement method is extended with minimum modification in the sensing front end to characterize the substrate noise. The implemented structure achieves the voltage...
Characterization of I/O channels in 3D package systems is quite challenging as it is difficult to observe signal quality. A traditional way of measuring each device in a component level does not capture complex interaction in 3D integration. Although a sense line can be designed to externally measure noise on power lines, it is not feasible for signal lines as it significantly alters the signal quality...
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