The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Recently, tapping into renewable energy sources has shown great promise in alleviating server energy poverty and reducing IT carbon footprint. Due to the limited, time-varying green power generation, matching server power demand to runtime power budget is often crucial in green data centers. However, existing studies mainly focus on the temporal variability of the power supply and demand, while largely...
Vertex-centric graph computations are widely used in many machine learning and data mining applications that operate on graph data structures. This paper presents GraphGen, a vertex-centric framework that targets FPGA for hardware acceleration of graph computations. GraphGen accepts a vertex-centric graph specification and automatically compiles it onto an application-specific synthesized graph processor...
Memristor, the fourth basic circuit element, has shown great potential in neuromorphic circuit design for its unique synapse-like feature. However, though the continuous resistance state of memristor has been expected, obtaining and maintaining an arbitrary intermediate state cannot be well controlled in nowadays memristive system. In addition, the stochastic switching behaviors have been widely observed...
Stereo vision is a well-known technique for acquiring depth information. In this paper, we present an FPGA-based real-time high-quality stereo vision system. By using AD-Census cost initialization, cross-based aggregation and semi-global optimization, the system provides high-quality depth results for highdefinition images. This is the first complete real-time hardware system that supports both cost...
Subsequence similarity search is one of the most common subroutines in time series data mining algorithms. According to previous studies, Dynamic Time Warping (DTW) distance is the best distance measurement in many domains. However, the high computational complexity of DTW distance makes it a critical bottleneck in many subsequence similarity search applications. In some applications, the performance...
Brush less DC motor has been more and more widely used in recent years. This paper designed a control system of BLDC motor driver Based on TMS320F2808 DSP, which can realize the closed loop control of current, velocity and position. Customer can set parameters and working mode of the driver with different load and use via the interface on PC, this paper discusses the main modules such as initialization,...
In many application domains, data are represented using large graphs involving millions of vertices and billions of edges. Graph exploration algorithms, such as breadth-first search (BFS), are largely dominated by memory latency and are challenging to process efficiently. In this paper, we present a reconfigurable hardware methodology for efficient parallel processing of large-scale graph exploration...
The electronics software and hardware design based on CCD47-10 is introduced in this article, including CCD output signal analog amplification, sequential driver, image data acquisition, SDRAM board data buffer and USB bus data transfer. The clear image exposed by LED is taken by the DAQ system in test.
The paper employed some independently developed sensors based on the Octopus X platform to build a Zigbee-based Sensor Networks. Also, we implemented a Location-aware living environment by deploying the developed Zigee-based sensor. Besides, through the created window console interface, the sensed data can be transmitted and transformed to the database for further utilized. Moreover, by the devised...
The research on complex Brain Networks plays a vital role in understanding the connectivity patterns of the human brain and disease-related alterations. Recent studies have suggested a noninvasive way to model and analyze human brain networks by using multi-modal imaging and graph theoretical approaches. Both the construction and analysis of the Brain Networks require tremendous computation. As a...
Due to the growing demand of transmission capacity of the wireless communication system, multiple-input multiple-output orthogonal-frequency-division-multiplexing (MIMO-OFDM) communication system requires more and more MIMO antennas and a large number of OFDM subcarriers. Thus, the QR decomposition becomes one of the computational bottlenecks in the QR-based MIMO detection. The proposed Givens-Rotation-based...
Google's famous PageRank algorithm is widely used to determine the importance of web pages in search engines. Given the large number of web pages on the World Wide Web, efficient computation of PageRank becomes a challenging problem. We accelerated the power method for computing PageRank on AMD GPUs. The core component of the power method is the Sparse Matrix-Vector Multiplication (SpMV). Its performance...
As the scale of computer clusters and supercomputers is getting larger, the problem of power consumption and heat dissipation has become the biggest obstacle for the ever growing need for computation. Designing platforms for specific applications using the reconfigurable logic such as Field Programmable Gate Arrays (FPGAs) or highly parallel processors such as Graphic Processing Units (GPUs) will...
This paper presents a modified pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture. The canonic signed digit (CSD) representation is used to design the function of complex multiplier, which is the main function block in the FFT processor. The processor of a 16-bit 16-point pipeline FFT is realized on the Xilinx Virtex-4 FPGAs. The achieved maximum clock frequency is...
NVIDIA CUDA and ATI Stream are the two major general-purpose GPU (GPGPU) computing technologies. We implemented RankBoost, a web relevance ranking algorithm, on both NVIDIA CUDA and ATI Stream platforms to accelerate the algorithm and illustrate the differences between these two technologies. It shows that the performances of GPU programs are highly dependent on the utilization of GPU's hardware memory...
In order to reduce test and repair cost in advanced system-on-chip products, wireless built-in self-repair (BISR) techniques for embedded memories are proposed in this paper. The redundant memory is divided into spare rows, spare column group blocks, and spare words which are used to replace faulty cells in the main memory. Based on this redundancy architecture, a BISR scheme suitable for built-in...
E-commerce (EC) over open devices and networks poses security challenges of a new dimension. This article presents a multi-party contract signing (MPCS) protocol to demonstrate how to apply the secure EC protocols to trading terminals supported by trusted computing (TC) technology. The protocol here reduces the number of rounds to two and the message transmission number to O(n2), which is the best...
In this paper, we propose block-level replacement techniques for content-addressable memories. The CAM array is first divided into row banks and column banks. Then, for each divided array (the overlapped CAM cells of a row bank and a column bank), two redundant row blocks are added and reconfiguration is performed at the block level instead of the conventional word level. According to simulation results,...
We propose a highly scalable image coder based on Zero-blocks and Array structures, called S-EZBA. It achieves not only distortion scalability, resolution scalability, and region of interest (ROI) retrievability, but also much of cost saving. We use a new formation of the final bitstream to realize these properties. Comparing with S-SPECK, S-EZBA omits memory needed on distributing the coding bits...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.