The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The column access time of a 512Mb DDR3 SDRAM implemented in a 90nm dual-gate CMOS process is reduced by 2.9ns to 8.4ns through an 8:4 multiplexed data-transfer scheme that enables the use of shielded I/O lines. A dual-clock additive latency counter enables a 30% reduction in cycle time from 1.7 to 1.2ns. By combining these with a multiple on-die-termination merged output driver, 1.3Gb/s/pin operation...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.