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The growing reliance on intellectual properties exposes systems on chip (SoCs) to many security vulnerabilities and is raising more and more concerns. At the same time, with the quick increase in chip density and deep scaling of feature size, current billion-transistor chip designs introduce more challenges to manufacturing fault-free chips. In this paper, we propose an integrated run-time solution...
With the rapid increase in the number of processor cores on a chip, packet-switching networks on chip (NoCs) have emerged as a promising paradigm for designing scalable communication infrastructures for future multi-core processors. The quest for high-performance networks, however, has led to very area-consuming and complex routers with marginal return in performance. On the other hand, studies show...
Packet-switching networks on chip (NoCs) have emerged as a promising paradigm for designing scalable communication infrastructures for future chip multiprocessors and complex Systems on Chip (SoCs). However, the quest for highperformance networks has led to very area-consuming and complicated routers with little return in performance. This paper presents X-Network, a low-area and high-performance...
Prior studies on packet-switching on-chip networks have primarily focused on the micro architecture of the router to reduce the communication latency. In this paper, we propose a novel interconnection topology for mesh-connected processor arrays. By sharing routers among PEs and PEs among routers, our network significantly reduces the average hop count for a packet, thereby reducing the network latency...
With the rapid increase of processing elements (PEs) on a single chip, the communication network poses a major limiting factor for both performance and power consumption in future SoCs. This paper presents a low-area and low-latency wormhole-switching network on chip (NoC). By introducing a new PE-router organization, our design not only reduces the total number of routers for a given number of PEs,...
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